The present invention relates generally to fin field effect transistor structures and methods for fabricating those structures. Particularly, the invention relates to a semiconductor fin structure having oxidation induced stress within the channel of the semiconductor fin and methods for fabricating a semiconductor fin structure having oxidation-induced stress within the channel of the semiconductor fin.
As semiconductor technology continues to advance and semiconductor device and structure dimensions continue to decrease, the utilization of field effect transistor (FET) devices of the fin type rather than planar-type has increased. A fin-FET device is characterized by a semiconductor fin that is positioned perpendicularly with respect to a semiconductor substrate, to provide a vertical channel within the fin-FET device. This vertical channel, rather than an exclusively planar channel characteristic of a planar-FET device, is covered with a gate structure.
The performance of a modern microelectronic device is highly dependent on the collective speed of the FETs found within the device's integrated circuits. One factor that affects the speed of a FET is carrier mobility, which determines the flow of electric current through the FET's channel between the source and drain. Consequently, improving the carrier mobility of the FETs within a microelectronic device's integrated circuits enhances the device's performance. One method to increase the carrier mobility in a FET is trough applying mechanical stress to the channel of the FET.
Field Effect Transistors (FETs), which lay at the core of an integrated circuit, typically are characterized by being of a hole conduction type, called pFET, or being of an electron conduction type, called nFET. And just as the conduction type differs between an nFET and a pFET, the methods for increasing carrier mobility with them differs. Accordingly, in order to maximize the performance of both nFETs and pFETs within integrated circuit devices, the stress components should be engineered and applied differently for nFETs and pFETs because the type of stress that benefits the performance of an nFETs is generally disadvantageous for the performance of pFETs. More particularly, when a device is in tension the performance characteristics of an nFET are enhanced while the performance characteristics of a pFET are diminished.
To selectively create tensile stress in nFETs and compressive stress in pFETs, distinctive processes and different combinations of materials are used. For example, liners on gate sidewalls have been utilized to selectively induce the appropriate stress in the channels of the FET devices. By providing liners the appropriate strain is applied to the device. While this method does provide tensile stresses to nFET devices and compressive stresses along the longitudinal direction of pFET devices, they can require additional materials and more complex processing, and consequently are more expensive. Further, the stresses that can be applied utilizing liners are typically limited to moderate levels (i.e. on the order of 100s of MPa).
A method that has been implemented to increase the stress levels in a fin-FET device, is the creation of silicon-germanium (SiGe) lattice layers. When epitaxially grown on silicon, an unrelaxed SiGe layer will have a lattice constant that conforms to that of the silicon substrate. Upon relaxation though, the SiGe lattice constant approaches that of its intrinsic lattice constant which is larger than that of silicon. Accordingly, when a silicon layer is epitaxially grown thereon, the silicon layer conforms to the larger lattice constant of the relaxed SiGe layer which results in expansion via a physical biaxial stress to the silicon layer. This physical stress applied to the silicon layer is beneficial to nFET devices but degrades the performance of pFET devices.
Another method of inducing stress within the channel of a fin-FET device utilizes embedded stressor materials epitaxially formed in the source/drain regions of the device. The source/drain regions of the device are recessed while the channel is protected by the gate and spacers and a semiconductor with lattice constant different from that of the fin is epitaxially grown in the recess. If a semiconductor with equilibrium lattice constant larger than that of the fin is used, compressive stress is applied to the channel. Similarly, if a semiconductor with equilibrium lattice constant smaller than that of the fin is used, tensile stress is applied to the channel. Typically, SiGe and Si:C are used to apply compressive and tensile stress, respectively, to a Si channel.
However, as the transistor pitch is made smaller to obtain higher device density in advanced CMOS technologies, the volume available to form embedded source/drain stressors becomes smaller. Consequently, the amount of stress that can be applied to the channel of the transistor is reduced. Also, the three-dimensional structure of the fin-FET results in non-uniform stress distribution in the channel of the fin-FET. Typically, with embedded source/drain stressors maximum amount of stress is obtained at the top of the fin, where as stress is negligible at the bottom of the fin. So, there is a need to new stressor elements that are more efficient in inducing stress to the channel of Fin-FET devices.